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    Christophe F. Lair

    Christophe F. Lair

    T: +1.703.770.7797 F: +1.703.905.2500
    Email  |  Download vCard  | 
    Christophe Lair is a partner in the law firm's Intellectual Property practice and is located in the Northern Virginia office. He focuses on strategic intellectual property counseling, patent prosecution, dispute resolution, licensing, technology transactions, intellectual property mining and enforcement, reexaminations, reissue proceedings, and pre-litigation opinions. Mr. Lair represents U.S. and foreign clients in the areas of materials, physics, optics, semiconductors, mechanical tools, lithography, business methods, internet and software. Mr. Lair was seconded full-time for three and a half months to work in the corporate intellectual property department of one of the world's largest semiconductor equipment manufacturers in Europe.

    Prior to attending law school, Mr. Lair worked as a research engineer for STMicroelectronics in France and for the French atomic agency (CEA-DAM). During his career as an engineer and project leader, Mr. Lair worked on the development of a new generation of microchips discovered new processes of manufacturing for advanced microchips, and implemented new materials for advanced interconnects. He is knowledgeable in all semiconductor processes and semiconductor tools (processing tools: etching, spin coating, lithography, CVD and PVD deposition/ characterization tools: SEMCD, optical and electrical tools…) and spent a significant amount of time in clean rooms doing research. Mr. Lair has served as principal author on several articles in these areas for international conferences.


    American Intellectual Property Law Association

    Recent Patents

    “Process for Achieving Intermetallic and/or Intrametallic Air Isolation in an Integrated Circuit, and Integrated Circuit Obtained” – co-inventor with Jerome Alieu and Michel Haond. Patent No.: U.S. 6,812,113; Patent Issued: November 2, 2004

    External Publications

    "New method to study unlanded via architecture. Application to advanced interconnects: Al with Low k and copper dual damascene", International Interconnects Technology Conference, IITC'2000, San Francisco, California, 2000

    "Influence of HSQ dielectric on process conditions and impact on CMOS circuit performance", ESSDERC'1999, Leuven, Belgium, 1999

    "Integration of HSQ in a sub .2 micron CMOS technology with unlanded via architecture", VMIC'1999, Santa Clara, California, September 1999 (Outstanding Paper Award of the Conference)

    "Developing a 0.18-Micron CMOS Process", IEEE Micro, vol. 19, no. 5, pp16-22, September 1999

    "Planarization properties of hydrogen silsesquioxane (HSQ) influence on CMP", MAM'99 European Workshop on Materials for Advanced Metallization No. 3, Ostende , BELGIUM, 1999

    Proceedings 1998 VMIC conference, IMIC, Tampa, Florida, 1998

    Commonwealth of Virginia
    Registered to practice before the U.S. Patent and Trademark Office
    J.D., University of Maryland School of Law, 2003
    M.S., Material Sciences (DEA Sciences des Materiaux), Université Paris, 1996
    with honors
    M.S., Engineering with a specialization in Physics (diplôme d’ingénieur Physicien), Ecole Supérieure de Physique et de Chimie Industrielles de la ville de Paris, 1996
    B.S., Physics and Chemistry, University of Toulouse
    magna cum laude, ranked first in graduating class

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