Mr. Lair's intellectual property practice focuses on patent prosecution and client counseling. His experience includes:

• Draft patentability, invalidity, and non infringement opinions. Draft product clearances and perform due diligence analyses.
  

• Draft original applications. Prosecute domestic and PCT applications. Conduct personal and telephone interviews with PTO examiners.
  

• Draft appeals to the Board of Patent Appeals and argue appeals before the Board of Patent Appeals.
  

• Counsel corporate and individual inventor clients on patent procurement, enforcement, and defensive issues.
  

• Advise on intellectual property licensing and other transaction matters.

Mr. Lair has worked with various technologies, including semiconductors, materials (chemistry and physics of materials), mechanical tools, lithography, fuel cells, helicopter technology, optics, fiber optics, wireless communications, Internet, business methods and optical networks.  Mr. Lair was seconded full-time for three and a half months to work in the corporate intellectual property department of one of the world's largest semiconductor equipment manufacturers in Europe.

Prior to attending law school, Mr. Lair worked as a research engineer for STMicroelectronics in France and for the French atomic agency (CEA-DAM). During his career as an engineer and project leader, Mr. Lair worked on the development of a new generation of microchips discovered new processes of manufacturing for advanced microchips, and implemented new materials for advanced interconnects. He is knowledgeable on all semiconductor processes and semiconductor tools (processing tools: etching, spin coating, lithography, CVD and PVD deposition/ characterization tools: SEMCD, optical and electrical tools…) and spent a significant amount of time in clean rooms doing research. Mr. Lair has served as principal author on several articles in these areas for international conferences.

Affiliations

American Intellectual Property Law Association

Other Recognitions
Recent Patents

“Process for Achieving Intermetallic and/or Intrametallic Air Isolation in an Integrated Circuit, and Integrated Circuit Obtained” – co-inventor with Jerome Alieu and Michel Haond. Patent No.: U.S. 6,812,113; Patent Issued: November 2, 2004

External Publications

"New method to study unlanded via architecture. Application to advanced interconnects: Al with Low k and copper dual damascene", International Interconnects Technology Conference, IITC'2000, San Francisco, California, 2000

"Influence of HSQ dielectric on process conditions and impact on CMOS circuit performance", ESSDERC'1999, Leuven, Belgium, 1999

"Integration of HSQ in a sub .2 micron CMOS technology with unlanded via architecture", VMIC'1999, Santa Clara, California, September 1999 (Outstanding Paper Award of the Conference)

"Developing a 0.18-Micron CMOS Process", IEEE Micro, vol. 19, no. 5, pp16-22, September 1999

"Planarization properties of hydrogen silsesquioxane (HSQ) influence on CMP", MAM'99 European Workshop on Materials for Advanced Metallization No. 3, Ostende , BELGIUM, 1999

Proceedings 1998 VMIC conference, IMIC, Tampa, Florida, 1998