Exploring R&D Opportunities under the CHIPS Act

The CHIPS R&D Program
The Research and Development Office (R&D Office)—which sits within the National Institute of Standards and Technology (NIST)—is directed to work with semiconductor designers, manufacturers, academics and students to enhance the competitiveness of the U.S. semiconductor industry.

The $11 billion CHIPS Act investment will guide the creation of four integrated entities under the R&D Office’s purview who will work in a coordinated fashion to address cross-cutting industry issues, as follows:

• National Semiconductor Technology Center (NSTC)—the public-private consortium that serves as a focal point for semiconductor research.
• National Advanced Packaging Manufacturing Program—developing the capability to package chips together in multiple dimensions with a variety of functions.
• Manufacturing USA Institute(s)—the CHIPS Act will provide for up to three new Manufacturing USA institutes to advance the research and commercialization of semiconductor manufacturing technologies.
• Metrology R&D—the NIST will conduct measurement science critical to the development of new materials, packaging and production methods.

Each of these programs present opportunities for industry collaboration and many offer support in the form of funding or additional resources and data for semiconductor companies.

The National Semiconductor Technology Center
The cornerstone of the CHIPS R&D Office is the National Semiconductor Technology Center. The NSTC will be a nonprofit entity led by the NSTC Consortium made up of a Board of Trustees and CEO. The NSTC will consist of one headquarters connected to technical centers across the country that will leverage existing facilities and resources and build new facilities where needed. These technical centers, the highlight of the NSTC, will have capabilities for end-to-end fabrication as well as experimentation and testing that will be made available to industry in the region. In June of 2023, the Commerce Department announced the appointment of a Selection Committee that will appoint the Board of Trustees for the NSTC. In July, the Office announced that Jay Lewis would be joining NIST from Microsoft to serve as the Director for the NSTC Program at the R&D Office.

The NSTC is organized around the following three goals: 1) U.S. technology leadership, 2) managing assets that benefit the community and 3) workforce programs. The NSTC Vision Statement, released in April, announced a series of actions the NSTC can undertake to achieve these goals, including: identifying “Grand Challenges” facing the industry that the NSTC will work to solve; creating a cloud gateway to share datasets and patents; and finalizing a workforce development plan that will focus on recruiting, training and retaining semiconductor workers and engineers. The NSTC will connect semiconductor companies with critical technology available at the technical centers, and it will generate solutions in a collaborative space to improve R&D development.

The NSTC Investment Fund
The NSTC will also establish an Investment Fund that will support projects challenged by the high cost of requisite capital investment for early-stage semiconductor development. This could prove especially beneficial for startups. The Fund will be run by a manager with experience in private sector semiconductor investment and technology development. The manager has not yet been selected and more information on the fund’s direction will likely come from the soon-to-be-finalized Board of Trustees. The Fund will:

• Have a structure designed to help startups reduce risk and accelerate milestones in order to attract significant private capital;
• Collaborate with other U.S. Government entities that have similar objectives;
• Collaborate with investors that bring substantial expertise to assessing structuring finances;
• Use a portfolio approach which balances risk across investments; and
• Have entrepreneurial support.

In addition to the Investment Fund, the NSTC will also fund projects that align with its goal to achieve U.S. technology leadership. The NSTC will prioritize projects that would most benefit the industry in five to 15 years—prioritizing projects approaching a proof-of-concept stage to partner with the NSTC. 

Details on how the fund will operate, including how a company can apply for and receive funds, are likely to be established after the NSTC hires an Investment Fund manager.   

The NSTC Members
The NSTC Commission will be informed by member advisors who consist of general members, technical members and workforce members. The NSTC will have a flexible membership structure that scales fees to the size and capability of the member. The community invited to join the NSTC and help inform its decisions includes:

• Fabless semiconductor companies,
• Semiconductor customers who design their own chips,
• Research institutions and community colleges,
• State and local governments,
• Federal agencies, national labs and federally funded labs,
• Foundries and integrated device manufacturers,
• Equipment vendors and materials suppliers,
• Labor unions, and
• Investors.

Foreign entities of concern and entities owned, controlled by or subject to the jurisdiction of a foreign country of concern will not be eligible for membership.

Collaborating with the NSTC: Funding Opportunities and Resources for Next-Generation Technologies  

• National Advanced Packaging and Manufacturing Process (NAPMP). The NAPMP will be a separate funding program that can benefit companies working to onshore advanced packaging facilities. The NAPMP will prioritize funding for: 1) advanced packaging pilot facilities, modern and low volume facilities focused on packaging, and 2) heterogenous integrations technical centers, research institutions focused on integrating a wide variety of devices and materials from photonics to advanced node logic. Once a decision to fund a facility is made, the NAPMP will then work with the NSTC to determine whether that facility should be incorporated as one of the NSTC technical centers. Companies may be eligible for funding from the NAPMP program, or they can partner with the technology centers to build the next stage of semiconductor technology.
• Metrology Research Program. The Metrology Research Program will accelerate the development of microelectronics by carrying out metrology research focused on NIST-identified challenges and also by supplying the industry with reference data, reference materials and calibrations for precision equipment. Metrology is the ability to measure all aspects of the integrated circuit manufacturing process—metrology is essential to maximizing the semiconductor’s usefulness through a detailed understanding of how it functions. In June, NIST published a report on Metrology Gaps in the Semiconductor Ecosystem, which identified 10 focus areas that the Metrology Research Program would prioritize research in across automation, virtualization and security.  
• Manufacturing USA. Manufacturing USA is a network of 16 public-private partnerships that work together to solve challenges facing the advanced manufacturing industry. The mission of Manufacturing USA is to enhance U.S. competitiveness, encourage economic growth and bolster national security. Under the CHIPS Act, Manufacturing USA will create three new institutes focused exclusively on semiconductor manufacturing. These institutions will address the microelectronics innovation ecosystem in areas such as design, fabrication, advanced test, assembly and packaging capabilities. Based on comments to the October 2022 Request for Information, the public encouraged NIST to develop semiconductor institutes that would supplement other CHIPS R&D activities and that deployed a co-investment strategy to encourage participation from diverse stakeholders. Semiconductor companies are encouraged to participate in the further development and deployment of the Manufacturing USA centers through trainings, workforce opportunities and collaborative discussion addressing the ecosystem as a whole.
• Connecting Department of Defense and Department of Energy. The Department of Defense (DOD) Microelectronic Commons supports the semiconductor industry through its lab-to-fab pathway—connecting nine DOD designated technology Hubs with core facilities and fabs advancing microelectronics prototypes across six critical technology areas. A “Hub” is a designated network of entities with lab-prototyping capabilities and entities that provide microelectronic talent for lab-to-fab transitions of semiconductor technologies. The Hubs will be responsible for connecting research and designers to prototyping capabilities with the goal of addressing the “valley of death” that innovators can face when moving from proof of concept to prototype development and finally to commercialization. The DOD will award a total of $1.63 billion in project funding between FY 2023 and FY 2027 that the nine Hubs will compete for annually. The DOD recently closed its first Request for Solutions (RFS), during which a range of entities, including universities, semiconductor companies and national labs, applied to be designated as a regional Hub. The DOD has not yet selected the Hubs themselves.

Details are emerging on how the Hubs will operate once established. However, it appears that the Hubs will remain flexible to new members and partnership opportunities, meaning companies that did not apply during the RFS can likely still benefit from funding by joining a designated Hub, by participating in future project proposals with Hubs and through teaming opportunities. Companies further will be able to participate in multiple Hubs and work on multiple prototype projects.

The NSTC will work with the Commons to provide access to manufacturing technologies that support end-to-end wafer-level and die-level prototyping. 

The NSTC can also leverage the resources of the Department of Energy (DOE) Office of Science and the National Nuclear Security Administration to accelerate the deployment of next-generation semiconductor technologies. The NSTC can connect semiconductor companies with the DOE national laboratories and state-of-the-art technologies, such as x-ray light sources, neutron sources, nanoscale science centers and exascale computing abilities.

The NSTC also plans to work with the National Science Foundation to coordinate programming that bolsters the microelectronics workforce. For example, the Future of Semiconductors (FuSe) program, which is funding research teams practicing co-design approaches and education grants, can feed technology into the NSTC while actively encouraging the growth of the semiconductor workforce. Companies can engage with both programs or partner between the programs to maximize resources.

Whether it be for active CHIPS funding opportunities, guidance in the planning or formulation of relevant application compliance requirements, or for other CHIPS funding opportunities anticipated by the Commerce Department, Pillsbury’s Public Policy and International Trade teams are ready to help your company leverage CHIPS Act opportunities to expand your business.